1. Field of the Invention
The present invention is generally directed to microprocessor devices. In particular, the present invention relates to microprocessor devices which provide a hardware implementation of a loop.
2. Background
Conventional loop implementations use processor instructions to test for a defined condition. If the condition is met, a program counter indicating the address of the next instruction to be processed is configured with the address of the first instruction within the loop. The loop's instructions are processed until an instruction triggering the test is reached, and the process is repeated until the condition is no longer met. The need to test the condition and reconfigure the program counter adds overhead to the loop operation, and this overhead is incurred on each iteration through the loop. Testing the condition usually requires checking a counter, which must also be decremented each time the condition is tested, further increasing overhead. Loops are used in many applications, and such frequent usage compounds the effects of the loop overhead. Eliminating the loop overhead promotes speed benefits throughout most code.
One solution available in the art is the use of zero overhead loops (“ZOLs”). Zero overhead loops are typically implemented in processor systems using dedicated hardware created expressly for the purpose of eliminating loop overhead. Such implementations are sometimes found in digital signal processors (“DSPs”). A micro-architecture capable of natively supporting zero overhead loops is not always available, and is uncommon in many other processor systems.
Additional prior art solutions incorporate the use of branch target caches to reduce or eliminate inefficiencies caused by branching instructions. However, such prior art implementations require the filling of a branch target cache the first time an unexpected branch is encountered, resulting in overhead.
Accordingly, what is desired is a system and method that resolves the problem associated with the presence of decrement, test, and branch overhead by implementing ZOLs using an existing micro-architecture.